The circuit design for voltage/current control utilizing high-side FET and Low-side FET have many applications involving regulation of electrical power supplies of the integrated circuit. In such application, current flows from the junction between the source of high-side FET and the drain of low-side FET to the load. This load is connected in series with an inductor and in parallel with a capacitor. When the cycle of operation starts, the high-side FET is turned on and the low-side FET is turned off allowing current to flow from high-side FET to inductor, capacitor and load. This current increases as the capacitor charges. When the voltage across the load reaches the target level, the high-side FET is turned off and the low-side FET is turned on, and this current decreases as the capacitor discharges. Hence by switching the high side FET and low side FET alternatively between on and off, the output voltage will not changed due to the increase or decrease of the inductor current.
As shown in FIG. 1, the conventional switching controller consists of a comparator 10, a high-side FET 12 and a low-side FET 14. The drain of the high-side FET 12 is electrically connected to the input voltage VIN, and the source of the high-side FET 12 is connected to the drain of the low-side FET 14. The source of the low-side FET 14 is connected to ground. The gate of the high-side FET 12 and that of the low-side FET 14 are respectively connected to the comparator 10. When sufficient voltage is applied to the transistor gate electrode, corresponding current will flow between the drain and the source of the transistor. Through voltage/current control operation, the gate of high-side FET and that of low-side FET are alternately switched on and off. Furthermore, an inductor 16 is connected to the junction connecting the source of high-side FET 12 and the drain of the low-side FET 14. A load 18 is connected in series with the inductor and to ground, and the voltage across the load 18 is the output voltage Vo.
When the high-side FET 12 and the low-side FET 14 is about to switch from on to off or vice versa, the gate of the transistors will remain in the original state of on or off for some time. As such, a feedback voltage F is generated from the output voltage VO using a voltage divider 20. Furthermore, the adder 26 receives a periodic triangular wave signal from the source of the low-side FET and one end of the inductor 16. Adder 26 combines the feedback voltage F and the triangular wave signal together to generate a sum signal S. Comparator 10 compares this sum signal S with a target voltage T generated by a target voltage generator 22. When the sum signal S is equal to the target voltage T, comparator 10 generates a trigger signal to switch the high side FET 12 to off and low side FET 14 to on. In addition, a capacitor 24 is connected in parallel with load 18.
During load transient condition, for example when load 18 changes from overload to light load, the current in load 18 will decrease rapidly, and consequently the current in the inductor 16 will also decrease at the same time. Also when the high side FET 12 is turned off and the low side FET 14 is turned on, the voltage drop across the drain and the source of the low side FET 14 results in a trapezoidal wave signal. If the switching of the high side FET 12 and the low side FET 14 is cyclical, the trapezoidal wave signals are also cyclical. Since the triangular wave signal is formed by subtracting the end voltage of the trapezoidal wave of the previous cycle from the trapezoidal wave of the current cycle, and also because the absolute value of the end voltage of trapezoidal wave of the previous cycle is greater than the absolute value of the trapezoidal wave of the current cycle, the triangular wave will generate a negative voltage, thereby resulting in the sum signal S being less than the target voltage T, thus turning the high side FET on and providing energy to load 18, as such the output voltage increases. At the same time, because the load current 18 decreases rapidly, current will flow from the inductor 16 through the capacitor 24 to ground, causing the output voltage Vo to climb continuously resulting in an unstable phenomenon.
It is within this context that embodiments of the present invention arise.